View HSD128M72B9K_4631355.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HANBit
HSD128M72B9K
Synchronous DRAM Module 1024Mbyte (128Mx72Bit), 8K Ref., 3.3V ECC Unbuffered SO-DIMM,
Part No. HSD128M72B9K
GENERAL DESCRIPTION
The HSD128M72B9K is a 128M x 72 bit Synchronous Dynamic RAM high density memory module. The module consists of nine CMOS 128M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glassepoxy substrate. One or two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD128M72B9K is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
* JEDEC standard 3.3V power supply * Burst mode operation * Auto & self refresh capability (8192 Cycles/64ms) * LVTTL compatible with multiplexed address * Separate power and ground planes to improve immunity * Height : 1.250 inches * MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * The used device is 16M x 8bit x 4Banks Synchronous DRAM
* Part Identification HSD128M72B9K-F/10L : 100MHz (CL=3) HSD128M72B9K-F/10 : 100MHz (CL=2) HSD128M72B9K-F/12 : 125MHz (CL=3) HSD128M72B9K-F/13 : 133MHz (CL=3) ** F means Auto & Self refresh with Low-Power (3.3V)
URL : www.hbe.co.kr REV.0.0(January. 2003)
1
HANBit Electronics Co.,Ltd.
HANBit
PIN ASSIGNMENT
No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 Front Vss DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 Vss DQM0 DQM1 VCC A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 Vss CB0 CB1 No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 Back Vss DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 Vss DQM4 DQM5 VCC A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 VCC DQ44 DQ45 DQ46 DQ47 Vss CB4 CB5 No. 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 CKE0 VCC /CAS CKE1 A12 135 137 139 141 143 Front /CS1 NC Vss CB2 CB3 VCC DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 VCC A6 A8 Vss A9 A10_AP VCC DQM2 DQM3 Vss DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 Vss **SDA VCC No. 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
HSD128M72B9K
Back NC CLK1 Vss CB6 CB7 VCC DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 VCC A7 BA0 Vss BA1 A11 VCC DQM6 DQM7 Vss DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 Vss **SCL VCC
Voltage Key 61 63 65 67 69 CLK0 VCC /RAS /WE /CS0 62 64 66 68 70
** These pins should be NC in the system which does not support SPD
URL : www.hbe.co.kr REV.0.0(January. 2003)
2
HANBit Electronics Co.,Ltd.
HANBit
Functional Block Diagram
/CS1 /CS0 /CS /CS
HSD128M72B9K
DQM0 DQ(0:7) Add(0:12) BA(0:1) /RAS /CAS /WE CKE(0:1) CLK0
DQM DQ(0:7) BA(0:1) /RAS /CAS /WE CKE(0:1) CLK
/CS
DQM4 DQ(32:39)
DQM DQ(0:7)
/CS
Add(0:12)
Add(0:12) BA(0:1)
U1L
U1U
/RAS /CAS /WE CKE(0:1) CLK1 CLK
U5L
U5U
DQM1 DQ(8:15)
DQM
/CS
/CS
DQ(0:7) Add(0:12) BA(0:1) /RAS /CAS /WE CKE(0:1) CLK
DQM5 DQ(40:47)
DQM DQ(0:7)
/CS
/CS
Add(0:12) BA(0:1)
U2L
U2U
/RAS /CAS /WE CKE(0:1) CLK
U6L
U6U
DQM2 DQ(16:23)
DQM DQ(0:7)
/CS
/CS
DQM6 DQ(48:55)
DQM DQ(0:7)
/CS
/CS
Add(0:12) BA(0:1) /RAS /CAS /WE CKE(0:1) CLK
Add(0:12) BA(0:1)
U3L
U3U
/RAS /CAS /WE CKE(0:1) CLK
U7L
U7U
DQM3 DQ(24:31)
DQM DQ(0:7)
/CS
/CS
DQM7 DQ(56:63)
DQM
/CS
/CS
Add(0:12) BA(0:1) /RAS /CAS /WE CKE(0:1) CLK
DQ(0:7) Add(0:12) BA(0:1) /RAS /CAS /WE CKE(0:1) CLK
U4L
U4U
U8L
U8U
DQM1 CB(0:7)
DQM DQ(0:7)
/CS
/CS
Add(0:12) BA(0:1) /RAS /CAS /WE CKE(0:1) CLK
Serial PD
U9L
U9U
SCL A0 A1 A2
SDA WP 47K SA0 SA1 SA2
VCC
One or two 0.1uF Capacitors per each SDRAM
To all SDRAMs
VSS
URL : www.hbe.co.kr REV.0.0(January. 2003)
3
HANBit Electronics Co.,Ltd.
HANBit
PIN FUNCTION DESCRIPTION
Pin CLK0~CLK1 /CS0~/CS1 Name System clock Chip select Input Function
HSD128M72B9K
Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Check bits for ECC Power and ground for the input buffers and the core logic.
CKE0, CKE1
Clock enable
A0 ~ A12 BA0 ~ BA1 /RAS /CAS /WE DQM0 ~ 7 DQ0 ~ 63 CB0~7 VCC / VSS
Address Bank select address Row address strobe Column address strobe Write enable Data input / output mask Data input / output Check bit Power supply / ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature Short Circuit Output Current Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. restricted to the conditions as detailed in the operational sections of this data sheet. rating conditions for extended periods may affect device reliability. Functional operation should be Exposure to absolute maximum SYMBOL VIN , VOUT Vcc PD TSTG IOS RATING -1V to 4.6V -1V to 4.6V 18W -55oC to 150oC 50mA
URL : www.hbe.co.kr REV.0.0(January. 2003)
4
HANBit Electronics Co.,Ltd.
HANBit
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input leakage current Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. SYMBOL Vcc VIH VIL VOH VOL I LI MIN 3.0 2.0 -0.3 2.4 -10 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4 10
HSD128M72B9K
UNIT V V V V V uA
NOTE 1 2 IOH = -2mA IOL = 2mA 3
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23 C, f = 1MHz, VREF =1.4V 200 mV) PARAMETER Input Capacitance (A0~A12, BA0~BA1) Input Capacitance (/RAS, /CAS, /WE) Input Capacitance (CKE0 ~ CKE1) Input Capacitance (CLK0 ~ CLK1) Input Capacitance (/CS0 ~ /CS1) Input Capacitance (DQM0 ~ DQM1) Data Input Capacitance (DQ0 ~ DQ63) Data Input Capacitance (CB0 ~ CB7) SYMBOL CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT MIN 45 45 35 25 35 10 15 15 MAX 90 90 60 45 60 25 30 30 UNITS pF pF pF pF pF pF pF pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70 C) PARAMETER Operating current (One bank active) SYMBOL TEST CONDITION Burst length = 1 ICC1 tRC tRC(min) IO = 0mA ICC2P ICC2PS CKE VIL(max) tCC=10ns CKE & CLK VIL(max) tCC= CKE VIH(min) Precharge standby current in non power-down mode ICC2N CS* VIH(min), time during 20ns tCC=10ns Input signals are changed one 360 mA 36 36 mA mA 1080 990 990 990 mA 1 VERSION -13 -12 -10 -10L UNIT NOTE
Precharge standby current in power-down mode
URL : www.hbe.co.kr REV.0.0(January. 2003)
5
HANBit Electronics Co.,Ltd.
HANBit
CKE VIH(min) ICC2NS ICC3P ICC3PS CLK VIL(max), tCC= Input signals are stable Active standby current in CKE VIL(max), tCC=10ns CKE&CLK VIL(max) tCC= CKEVIH(min), Active standby current in non power-down mode (One bank active) ICC3NS ICC3N CS*VIH(min), tCC=10ns Input signals are changed one time during 20ns CKEVIH(min) CLK VIL(max), tCC= Input signals are stable IO = 0 mA Operating current (Burst mode) Refresh current Self refresh current Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). ICC4 Page burst 4Banks Activated tCCD = 2CLKs ICC5 ICC6 tRC tRC(min) CKE 0.2V 2160 1980 1260 1260 315 450 72 72 180
HSD128M72B9K
power-down mode
mA
mA
1170
1170
mA
1
1890
1890
mA mA mA
2 3 4
54 27
AC OPERATING TEST CONDITIONS
(Vcc = 3.3V 0.3V, TA = 0 to 70 C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition +3.3V Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 UNIT V V ns V
Vtt=1.4V
1200W DOUT 870W 50pF* VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 1) DC output load (Fig. 2) AC output load circuit 50W DOUT Z0=50W 50pF
URL : www.hbe.co.kr REV.0.0(January. 2003)
6
HANBit Electronics Co.,Ltd.
HANBit
HSD128M72B9K
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) PARAMETER Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . (Recommand : tRDL=2CLK and tDAL=2CLK & 20ns.) SYMBOL tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max)
tRC(min)
VERSION -13 15 20 20 45 -12 16 20 20 48 100 65 68 2 2 CLK + tRP 1 1 1 2 1 70 70 -10 20 20 20 50 -10L 20 20 20 50
UNIT ns ns ns ns ns ns CLK CLK CLK CLK ea
NOTE 1 1 1 1
1 2.5 5 2 2 3 4
tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) PARAMETER CAS CLK cycle time latency=3 CAS latency=2 CAS CLK to valid output delay Output data hold time latency=3 CAS latency=2 CAS latency=3 tOH 2.7 tSAC 3 3 6 3 7 ns 2 tCC 5.4 SYMBOL -13 MIN 7.5 1000 6 MAX MIN 8 1000 10 6 -12 MAX MIN 10 1000 12 6 ns 1,2 -10 MAX MIN 10 1000 ns 1 -10L MAX UNIT NOTE
URL : www.hbe.co.kr REV.0.0(January. 2003)
7
HANBit Electronics Co.,Ltd.
HANBit
CAS latency=2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS CLK to output in Hi-Z Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. latency=3 CAS latency=2 tSHZ 6 tCH tCL tSS tSH tSLZ 2.5 2.5 1.5 0.8 1 5.4 3 3 2 1 1 6 3 3 3 2 1 1 6 3 3 3 2 1 1
HSD128M72B9K
ns ns ns ns ns 6 7 ns ns
3 3 3 3 3 2
If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter.
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode register set Auto refresh Refresh Self refresh Entry Exit CKE n-1 H H L H H CKE n X H L H X X /CS L L L H L L /RAS /CAS /WE DQM L L H X L H L L H X H L L H H X H H X X X X X V V BA0,1 A10/AP OP code X X Row address L H Column Address (A0 ~ A9) Column Auto precharge disable Auto precharge disable Burst Stop Precharge Bank selection All banks Entry Exit Entry Exit H H H L H L H X X L H L H L L H L X H L H L L L X V X X H X V X H H X V X X H X V L L X V X X H X V X X X X X X X V X
HANBit Electronics Co.,Ltd.
A11,A12, A9~A0
NOTE 1,2 3 3 3 3 4 4,5
Bank active & row addr. Read & column address Write & column address Auto precharge disable Auto precharge disable
H
X
L
H
L
L
X
V
L H X
Address (A0 ~ A9)
4 4,5 6
V X
L H X
X
Clock suspend or active power down
Precharge power down mode DQM
URL : www.hbe.co.kr REV.0.0(January. 2003)
7
8
HANBit
No operation command H X H L X H X H X H X
HSD128M72B9K
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
URL : www.hbe.co.kr REV.0.0(January. 2003)
9
HANBit Electronics Co.,Ltd.
HANBit
PACKAGING INFORMATION
Unit : mm
HSD128M72B9K
PCB Thickness: 1.0 0.1mm Tolerances : 0.15 unless otherwise specified Immersion Gold PCB Pattern
URL : www.hbe.co.kr REV.0.0(January. 2003)
10
HANBit Electronics Co.,Ltd.
HANBit
ORDERING INFORMATION
HSD128M72B9K
Part Number
Density
Org.
Package
Ref.
Vcc
Bank
MAX.frq CL3 133MHz CL3 125MHz CL3 100MHz CL2 100MHz CL3 133MHz CL3 125MHz CL3 100MHz CL2 100MHz
HSD128M72B9K-13 HSD128M72B9K-12 HSD128M72B9K-10L HSD128M72B9K-10 HSD128M72B9K-F13 HSD128M72B9K-F12 HSD128M72B9K-F10L HSD128M72B9K-F10
1024MByte 1024MByte 1024MByte 1024MByte 1024MByte 1024MByte 1024MByte 1024MByte
128M x 72 128M x 72 128M x 72 128M x 72 128M x 72 128M x 72 128M x 72 128M x 72
144 Pin-SODIMM 144 Pin-SODIMM 144 Pin-SODIMM 144 Pin-SODIMM 144 Pin-SODIMM 144 Pin-SODIMM 144 Pin-SODIMM 144 Pin-SODIMM
8K 8K 8K 8K 8K 8K 8K 8K
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
4Bank 4Bank 4Bank 4Bank 4Bank 4Bank 4Bank 4Bank
F means Auto & Self refresh with Low-Power (3.3V)
URL : www.hbe.co.kr REV.0.0(January. 2003)
11
HANBit Electronics Co.,Ltd.

▲Up To Search▲

Price & Availability of HSD128M72B9K

	To Download HSD128M72B9K Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .